1. Field of the Invention
The invention relates in general to a method for reducing the antenna effect, which occurs during plasma etching as would be performed during semiconductor device fabrication. In particular, the invention relates to a method employing a trench effect capable of substantially eliminating permanent damage to gate oxides in semiconductor devices, caused by the antenna effect during plasma etching fabrication.
2. Description of Related Art
Plasma etching is a technique widely utilized in the fabrication of VLSI (very large scale integration) semiconductor integrated circuit devices. In a plasma-filled environment, reactive ions generated in an ion discharge are accelerated by an electric field and collide with the wafer surface carrying the semiconductor device being fabricated. This is a high energy bombardment that well achieves the desired anisotropic etching characteristics for the device wafer being processed.
The plasma etching, however, also causes certain undesirable damage to the wafer. Glow discharge naturally results in electric charging in some regions over the wafer surface. Such charging is insignificant under normal conditions. However, if this charging occurs in a conductive layer region (for example, at the polysilicon gate) formed over the surface of the wafer, the resulting "antenna effect" causes excessive current by which the characteristics of a gate oxide layer located beneath the conductive layer can be severely degraded. The antenna effect occurs when interconnection conduction lines act as "antennas," amplifying the charging effect. One obvious reason for the vulnerability of gate oxide layers to such charging is that these layers are frequently fabricated as thin layers that may well be destructively penetrated if an electric field with excessive intensity as would cause a flow-through current, is present. This plasma-induced gate oxide damage is an critical issue in VLSI semiconductor fabrication processing.
In their paper, "Dielectric Breakdown of Gate Insulator due to RIE", Solid State Technology, April, 1984, p. 213, T. Watanabe and Y. Yoshida first reported the phenomenon of oxide damage during plasma etching procedures. A model was later proposed by Fang, S. Murakawa and J. P. McVittie in their paper "A New Model of Thin Oxide Degradation from Wafer Charging in Plasma Etching", Tech. Dig. IEDM 1992, at p. 61, in order to explain the mechanism responsible for such plasma-induced oxide damage. In the Fang et al. model, the plasma etching process that leads to the damage caused by electric charge build-up can be generally described as occurring in a sequence of three stages. FIGS. 1 to 3 of the accompanying drawings respectively schematically depict cross-sectional views respectively of a semiconductor device being plasma-etched in these three stages of the model of Fang et al.
FIG. 1 is a cross-sectional view of a semiconductor device in the initial stage of a conventional plasma etching procedure. Referring to FIG. 1, there is shown a silicon substrate 10 carrying semiconductor circuitry components such as the polysilicon gate structure. It may be observed that damage, caused by charge build-up in regions (if any) over the surface of the device wafer at this stage is barely possible. Such damage is rare because a doped polysilicon layer 12, most of which is to be subsequently etched away, still covers the entire surface area of the wafer. As the layer 12 is being etched by the plasma gas to form a doped polysilicon gate layer, non-uniformity of the plasma causes locally unbalanced ion and electron currents, which are signified by the positively- and negatively-signed arrows in the plasma ambient schematically shown in the drawing. During most of the actual etching process, the layer of polysilicon layer 12 continues to cover the wafer completely. The exposed polysilicon layer 12 therefore provides a low electrical resistance path across the surface of the device wafer so that surface currents can flow and balance the local non-uniformity in conduction current originating from the plasma. Therefore, virtually no charge can build up during this stage, and, accordingly, no oxide damage occurs.
In other words, the electric current induced by the presence of the ionized plasma ambient is able to flow without difficulty and discharge via the polysilicon layer 12, as is schematically shown in the drawing by the arrows pointing from the plasma ambient into and horizontally along the polysilicon layer 12. Thus, electrical charges are well prevented from accumulating over any of the surface regions of the device wafer in this stage of the plasma etching procedure.
Thus, during the initial stage of a plasma etching procedure when the coverage of the polysilicon layer 12 is still mostly intact, the electrically charged plasma ambient poses no threat to the semiconductor structure of the wafer, including the vulnerable oxide layer 18 that is to become part of the gate of a fabricated device. As is seen in FIG. 1, the gate oxide layer 18 is beneath the polysilicon layer 12 and is defined geometrically by the shape of a photoresist layer 14, as well as field oxide layers 16 surrounding it.
FIG. 2 shows a cross-sectional view of the semiconductor device of FIG. 1 in a following stage, near the conclusion of the plasma etching procedure. Referring to FIG. 2, as the etching procedure continues, the exposed regions of the polysilicon layer 12 are eventually consumed, forming isolation regions 13. That is, the isolation regions 13 are those portions in the etched polysilicon layer 12 that are completely consumed before other portions, due to the fact, for example, that the polysilicon layer is not of completely uniform thickness, so that thinner portions are consumed earlier.
The regions 13 cut the polysilicon layer 12 into independent island regions that include gate polysilicon layer 12' beneath the photoresist layer 14. Thus, the long surface conduction paths across the device wafer eventually become electrically resistive, or discontinuous, so that surface current paths that were convenient for electrical discharge are now broken. Meanwhile, gate electrode islands start to appear, and the phenomenon of local charge build-up may well begin.
At this stage, the discontinuities in the surface conduction paths across the surface of the device wafer begin to block the smooth discharge of electrical charges that may have accumulated, as the polysilicon layer 12 is gradually consumed and forms islands that are isolated from each other. This is schematically signified in the drawing by the positive charge signs above the surface of the polysilicon layer 12. Accumulation of such charges eventually establishes significant electric potential fields between the polysilicon layer 12 and the silicon substrate 10. When the level of the electric field approaches a certain threshold, an undesirable current discharge will commence, most likely through the vulnerable gate oxide layer 18.
Essentially, when the gate is sufficiently charged, sufficient Fowler-Nordheim tunneling current to induce permanent damage to the gate oxide 18 will occur, leaving the device being thus fabricated unsatisfactory for its designed use. The electric charge ratio is determined by factors that include the net local current imbalance and the amount of exposed gate area in the islands. The positive charge from the charge current is collected in the halo region in the polysilicon layer 12, around the gate island.
However, in a third, overetching stage of the plasma etching procedure, as is depicted in FIG. 3, the electrical charging phenomenon present in the second stage goes away. This is explained as follows.
Referring to FIG. 3, during the overetching stage, the halo region around the gate island in the etched gate polysilicon layer 12 eventually disappears. Only gate electrode edges, or sidewalls 19, of the gate polysilicon layer 12' are now exposed to the etching plasma ambient. All other portions of the polysilicon layer 12, external to the gate structure, are now completely consumed by the etching. Charge collection decreases significantly because of the small sidewall surface area of the gate electrode. Further damage to the gate oxide is thus unlikely beyond this stage of the plasma etching procedure.
The gate oxide damage arising in the above-described second (near-conclusion) stage is generally known to result from the antenna effect. From the mechanism described by Fang et al., it is apparent that the antenna effect mainly results from the collection of charge in the halo region of the polysilicon layer around the gate structure when the plasma etching procedure is in its near-conclusion stage. The non-uniformity of charge distribution in the plasma ambient does not cause charge build-up during either of the initial and overetching stages of the etching procedure. This model developed by Fang et al. is reasonably supported by plasma measurement results and SPICE simulations, as well as by examinations of damage resulting from plasma etching.
It is also important to note that the type of oxide damage that would be expected to occur during etching of polysilicon according to the above model, would also be expected to occur during plasma etching of other conductors, including, for example, aluminum layer. Further, non-uniformity in a plasma (which is the primary cause of the antenna effect) is not limited to RIE (reactive ion etching) and MERIE (magnetically-enhanced reactive ion etching) plasma etching reactors. It can also occur in advanced high density plasma(HDP) reactors, such as electron-cyclotron resonance (ECR) reactors, as well as in inductively-coupled plasma (ICP) reactors.
To solve the problem of antenna effect-induced oxide damage during plasma etching in VLSI semiconductor device fabrication, various approaches have been taken. For example, one approach is to reduce the excitation frequency during ion discharge; another is to modify the electrode design. These approaches, however, are unable to completely remedy the non-uniformity of charge distribution in the plasma ambient which leads to the antenna effect.
Another method that has been tried involves attempts to improve the oxide quality so that it can withstand the antenna-effect-induced damage. However, improvement of oxide quality beyond that necessary for the normal operation of the fabricated semiconductor device would require additional device fabrication process steps that increase both the complexity and the cost of the fabricated device.
Other methods have utilized circuit design techniques to limit the conductive area or edge. This approach, however, places restrictions on the flexibility of semiconductor circuit design, and the circuitry layout is inevitably larger, which conflicts with the trend toward further device miniaturization.
For example, U.S. Pat. No. 5,350,710 entitled "Device for Preventing Antenna Effect on Circuit" issued to United Microelectronics Corporation of Taiwan on Sep. 27, 1994, as well as U.S. Pat. No. 5,425,843 entitled "Process for Semiconductor Device Etch Damage Reduction Using Hydrogen-containing Plasma" issued to Hewlett-Packard Company of the U.S.A. on Jun. 20, 1995, disclose circuit techniques and post-treatment procedures used to solve the plasma damage problem. Results of these techniques and procedures, however, have failed to completely eliminate oxide damage and at the same time have increased the complexity of, and imposed more limitations on, the fabrication processes.